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Saturday, 6 February 2016

Decoupling Caps Placement in Embedded Hardware Boards

Board Level Decoupling

Decoupling the Power Distribution Network of the micro controller IC is critical to the PCB design process, because careful selection of the decoupling capacitors and placement has a big influence on the high speed performance of the board, and can reduce the emissions.

The on-board decoupling capacitors have an effective range of 1MHz – 200MHz. The range above 200MHz can be covered by using power plane capacitance. The effectiveness of the decoupling capacitors depends on the optimum placement and connection type.  

  • Place capacitors as close as possible to the µC.  
  • Keep the interconnection inductance of capacitors to the µC as low as possible.  
  • Use low effective series resistance and inductance (ESR and ESL) capacitors. − Since parasitic inductance is the limiting factor of the capacitor response to high frequency demand of current from the device, the ESL of the capacitor and the connection inductance should be selected so that the optimum value for the design is reached.  
  • Connect capacitors with vias close to the side of the pads. − Use side placement of the vias to reduce the current loop.
Connection of decaps
  • Dual vias can be used to reduce the parasitic inductance.  
  • Solder lands, traces and vias should be optimized for capacitor placement.
  • Do not use long traces to connect capacitors to GND or to VDD. − Always keep the return path of the high frequency current (lowest inductance path) small.
  • Select the smallest package available for the capacitors. − Select capacitors of type: ceramic multilayer X7R or X5R.  
  • To reduce the radiation / coupling from the oscillator circuit, a separated ground island on the GND layer should be made. This ground island can be connected at one point to the GND layer.
              − This helps to keep noise generated by the oscillator circuit locally on this separated island.
              − The ground connections of the load capacitors and VSSOSC should also be                connected to this island.
              − Traces for the load capacitors and Xtal should be as short as possible.

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